Freescale Semiconductor, Inc.
Inter-IC Bus
.
IBDR — IIC Bus Data I/O Register
$00E4
Bit 7
D7
0
6
D6
0
5
D5
0
4
D4
0
3
D3
0
2
D2
0
1
D1
0
Bit 0
D0
0
High
RESET:
Read and write anytime
In master transmit mode, when data is written to the IBDR a data transfer
is initiated. The most significant bit is sent first. In master receive mode,
reading this register initiates next byte data receiving. In slave mode, the
same functions are available after an address match has occurred.
NOTE: In master transmit mode, the first byte of data written to IBDR following
assertion of MS/SL is used for the address transfer and should comprise
of the calling address (in position D7-D1) concatenated with the required
R/W bit (in position D0).
IBPURD — Pull-Up and Reduced Drive for Port IB
$00E5
Bit 7
6
0
0
5
0
0
4
RDPIB
0
3
0
0
2
0
0
1
0
0
Bit 0
PUPIB
0
0
0
RESET:
Read and write anytime
RDPIB — Reduced Drive of Port IB
0 = All port IB output pins have full drive enabled.
1 = All port IB output pins have reduced drive capability.
PUPIB — Pull-Up Port IB Enable
0 = Port IB pull-ups are disabled.
1 = Enable pull-up devices for port IB input pins [7:4]. Pull-ups for
port IB input pins [3:0] are always enabled.
Technical Data
MC68HC912DG128 — Rev 3.0
Inter-IC Bus
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