Freescale Semiconductor, Inc.
Inter-IC Bus
IIC Protocol
15.5.6 Arbitration Procedure
IIC is a true multi-master bus that allows more than one master to be
connected on it. If two or more masters try to control the bus at the same
time, a clock synchronization procedure determines the bus clock, for
which the low period is equal to the longest clock low period and the high
is equal to the shortest one among the masters. The relative priority of
the contending masters is determined by a data arbitration procedure, a
bus master loses arbitration if it transmits logic “1” while another master
transmits logic “0”. The losing masters immediately switch over to slave
receive mode and stop driving SDA output. In this case the transition
from master to slave mode does not generate a STOP condition.
Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
15.5.7 Clock Synchronization
Since wire-AND logic is performed on SCL line, a high-to-low transition
on SCL line affects all the devices connected on the bus. The devices
start counting their low period and once a device’s clock has gone low, it
holds the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of the
SCL line if another device clock is still within its low period. Therefore,
synchronized clock SCL is held low by the device with the longest low
period. Devices with shorter low periods enter a high wait state during this
time (see Figure 15-3). When all devices concerned have counted off
their low period, the synchronized clock SCL line is released and pulled
high. There is then no difference between the device clocks and the state
of the SCL line and all the devices start counting their high periods. The
first device to complete its high period pulls the SCL line low again.
MC68HC912DG128 — Rev 3.0
Technical Data
Inter-IC Bus
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