Freescale Semiconductor, Inc.
Clock Functions
Bit 7
0
6
0
0
5
0
0
4
0
0
3
0
0
2
REFDV2
0
1
REFDV1
0
Bit 0
REFDV0
0
RESET:
0
REFDV — Reference Divider Register
$0039
Read anytime, write anytime, except when BCSP = 1.
The reference divider bits provides a finer granularity for the PLL
multiplier steps. The reference frequency is divided by REFDV + 1.
Bit 7
6
5
4
3
2
1
Bit 0
TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0
RESET:
0
0
0
0
0
0
0
0
CGTFLG — Clock Generator Test Register
$003A
Always reads zero, except in test modes.
Bit 7
LOCKIF
0
6
LOCK
0
5
0
0
4
0
0
3
0
0
2
0
0
1
LHIF
0
Bit 0
LHOME
0
RESET:
PLLFLG — PLL Flags
$003B
Read anytime, refer to each bit for write conditions.
LOCKIF — PLL Lock Interrupt Flag
0 = No change in LOCK bit.
1 = LOCK condition has changed, either from a locked state to an
unlocked state or vice versa.
To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home
mode.
Technical Data
MC68HC912DG128 — Rev 3.0
Clock Functions
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