Freescale Semiconductor, Inc.
Bus Control and Input/Output
Bit 7
DDE7
0
6
DDE6
0
5
DDE5
0
4
DDE4
0
3
DDE3
0
2
DDE2
0
1
0
0
Bit 0
0
0
RESET:
DDRE — Port E Data Direction Register
$0009
This register determines the primary direction for each port E pin
configured as general-purpose I/O.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
PE[1:0] are associated with XIRQ and IRQ and cannot be configured as
outputs. These pins can be read regardless of whether the alternate
interrupt functions are enabled.
This register is not in the map in peripheral mode and expanded modes
while the EME control bit is set.
Read and write anytime.
BIT 7
6
5
4
3
2
1
BIT 0
NDBE
CGMTE
PIPOE
NECLK
LSTRE
RDWE
CALE
DBENE
Normal
Expanded
RESET:
0
0
0
0
0
0
0
0
Special
Expanded
RESET:
RESET:
RESET:
0
1
1
0
1
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
Peripheral
Normal
single chip
Special
single chip
RESET:
0
0
1
0
1
1
0
0
PEAR — Port E Assignment Register
$000A
The PEAR register is used to choose between the general-purpose I/O
functions and the alternate bus control functions of Port E. When an
Technical Data
MC68HC912DG128 — Rev 3.0
Bus Control and Input/Output
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