Freescale Semiconductor, Inc.
Bus Control and Input/Output
Registers
alternate control function is selected, the associated DDRE bits are
overridden.
The reset condition of this register depends on the mode of operation
because bus -control signals are needed immediately after reset in some
modes.
In normal single-chip mode, no external bus control signals are needed
so all of port E is configured for general-purpose I/O.
In normal expanded modes, the reset vector is located in external
memory. The DBE and E clock are required for de-multiplexing address
and data, but LSTRB and R/W are only needed by the system when
there are external writable resources. Therefore in normal expanded
modes, only the DBE and E clock are configured for their alternate bus
control functions and the other bits of port E are configured for general-
purpose I/O. If the normal expanded system needs any other bus-control
signals, PEAR would need to be written before any access that needed
the additional signals.
In special expanded modes, DBE, IPIPE1, IPIPE0, E, LSTRB, and R/W
are configured as bus-control signals.
In special single chip modes, DBE, IPIPE1, IPIPE0, E, LSTRB, R/W, and
CALE are configured as bus-control signals.
In peripheral mode, the PEAR register is not accessible for reads or
writes. However, the CGMTE control bit is reset to one to configure PE6
as a test output from the PLL module.
NDBE — No Data Bus Enable
Normal: write once; Special: write anytime EXCEPT the first. Read
anytime.
0 = PE7 is used for DBE, external control of data enable on
memories, or inverted E clock.
1 = PE7 is the CAL function if CALE bit is set in PEAR register or
general-purpose I/O.
MC68HC912DG128 — Rev 3.0
Technical Data
Bus Control and Input/Output
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