Freescale Semiconductor, Inc.
Bus Control and Input/Output
Registers
BIT 7
PE7
—
6
5
4
3
2
1
BIT 0
PE0
—
PE6
—
PE5
—
PE4
—
PE3
—
PE2
—
PE1
—
RESET:
DBE or
ECLK or
CAL
MODB or
IPIPE1 or
CGMTST
Alt. Pin
Function
MODA or
IPIPE0
LSTRB or
TAGLO
ECLK
R/W
IRQ
XIRQ
PORTE — Port E Register
$0008
This register is associated with external bus control signals and interrupt
inputs, including data bus enable (DBE), mode select (MODB/IPIPE1,
MODA/IPIPE0), E clock, size (LSTRB), read/write (R/W), IRQ, and
XIRQ. When the associated pin is not used for one of these specific
functions, the pin can be used as general-purpose I/O. The port E
assignment register (PEAR) selects the function of each pin. DDRE
determines the primary direction of each port E pin when configured to
be general-purpose I/O.
Some of these pins have software selectable pull-ups (DBE, LSTRB,
R/W, IRQ, and XIRQ). A single control bit enables the pull-ups for all
these pins which are configured as inputs.
This register is not in the map in peripheral mode or expanded modes
when the EME bit is set.
Read and write anytime.
MC68HC912DG128 — Rev 3.0
Technical Data
Bus Control and Input/Output
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