Freescale Semiconductor, Inc.
Bus Control and Input/Output
that was accessed is on the low half of the data bus and the data for
address + 1 is on the high half of the data bus.
Figure 6-1. Access Type vs. Bus Control Pins
LSTRB
A0
0
R/W
Type of Access
1
0
1
0
0
1
1
0
0
1
8-bit read of an even address
8-bit read of an odd address
8-bit write of an even address
8-bit write of an odd address
16-bit read of an even address
1
0
1
0
16-bit read of an odd address
(low/high data swapped)
1
0
1
1
0
1
1
0
0
16-bit write to an even address
16-bit write to an even address
(low/high data swapped)
6.4 Registers
Not all registers are visible in the MC68HC912DG128 memory map
under certain conditions. In special peripheral mode the first 16 registers
associated with bus expansion are removed from the memory map.
In expanded modes, some or all of port A, port B, and port E are used
for expansion buses and control signals. In order to allow emulation of
the single-chip functions of these ports, some of these registers must be
rebuilt in an external port replacement unit. In any expanded mode, port
A, and port B, are used for address and data lines so registers for these
ports, as well as the data direction registers for these ports, are removed
from the on-chip memory map and become external accesses.
In any expanded mode, port E pins may be needed for bus control (e.g.,
ECLK, R/W). To regain the single-chip functions of port E, the emulate
port E (EME) control bit in the MODE register may be set. In this special
case of expanded mode and EME set, PORTE and DDRE registers are
removed from the on-chip memory map and become external accesses
so port E may be rebuilt externally.
Technical Data
MC68HC912DG128 — Rev 3.0
Bus Control and Input/Output
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