Freescale Semiconductor, Inc.
Bus Control and Input/Output
DBENE — DBE or Inverted E Clock on PE7
Normal modes: write once. Special modes: write anytime EXCEPT
the first; read anytime.
DBENE controls which signal is output on PE7 when NDBE control bit
is cleared. The inverted E clock output can be used to latch the
address for demultiplexing. It has the same behaviour as the E clock,
except it is inverted. Please note that in the case of idle expansion
bus, the ‘not E clock’ signal could stay high for many cycles.
The DBENE bit has no effect in single chip or peripheral modes and
PE7 is defaulted to the CAL function if the CALE bit is set in the PEAR
register or to an I/O otherwise.
0 = PE7 pin used for DBE external control of data enable on
memories in expanded modes when NDBE = 0
1 = PE7 pin used for inverted E clock output in expanded modes
when NDBE = 0
Bit 7
PUPK
0
6
PUPJ
0
5
PUPH
0
4
PUPE
1
3
0
0
2
0
0
1
PUPB
0
Bit 0
PUPA
0
RESET:
PUCR — Pull-Up Control Register
$000C
These bits select pull-up resistors for any pin in the corresponding port
that is currently configured as an input. This register is not in the map in
peripheral mode.
Read and write anytime.
PUPK — Pull-Up Port K Enable
0 = Port K pull-ups are disabled.
1 = Enable pull-up devices for all port K input pins.
PUPJ — Pull-Up or Pull-Down Port J Enable
0 = Port J resistive loads (pull-ups or pull-downs) are disabled.
1 = Enable resistive load devices (pull-ups or pull-downs) for all
port J input pins.
Technical Data
MC68HC912DG128 — Rev 3.0
Bus Control and Input/Output
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