Freescale Semiconductor, Inc.
Bus Control and Input/Output
Bit 7
PB7
—
6
5
4
3
2
1
Bit 0
PB0
—
Single Chip
RESET:
PB6
—
PB5
—
PB4
—
PB3
—
PB2
—
PB1
—
Expanded
& Periph:
ADDR7/
DATA7
ADDR6/
DATA6
ADDR5/
DATA5
ADDR4/
DATA4
ADDR3/
DATA3
ADDR2/
DATA2
ADDR1/
DATA1
ADDR0/
DATA0
Expanded
narrow
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
PORTB — Port B Register
$0001
Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0]
(except in narrow mode) respectively. When this port is not used for
external addresses such as in single-chip mode, these pins can be used
as general-purpose I/O. DDRB determines the primary direction of each
pin. This register is not in the on-chip map in expanded and peripheral
modes. Read and write anytime.
Bit 7
6
5
DDB5
0
4
DDB4
0
3
DDB3
0
2
DDB2
0
1
DDB1
0
Bit 0
DDB0
0
DDB7
0
DDB6
0
RESET:
DDRB — Port B Data Direction Register
$0003
This register determines the primary direction for each port B pin when
functioning as a general-purpose I/O port. DDRB is not in the on-chip
map in expanded and peripheral modes. Read and write anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
Technical Data
MC68HC912DG128 — Rev 3.0
Bus Control and Input/Output
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