Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
8.5.2 Enabling the Clock Monitor
Many applications require the clock monitor to determine if one of the
clock sources has become inactive, so the other can be used to recover
from a potentially dangerous situation. Using the clock monitor requires
both clocks to be active (ECGON and ICGON both set). To enable the
clock monitor, both clocks also must be stable (ECGS and ICGS both
set). This is to prevent the use of the clock monitor when a clock is first
turned on and potentially unstable.
Enabling the clock monitor and clock monitor interrupts requires a flow
similar to this flow:
1. Enable the alternate clock source
2. Wait for both clock sources to be stable
3. Switch to the desired clock source if necessary
4. Enable the clock monitor
5. Enable clock monitor interrupts
These events must happen in sequence. A short assembly code
example of how to employ this flow is shown in Figure 8-8. This code is
for illustrative purposes only and does not represent valid syntax for any
particular assembler.
;Clock Monitor Enabling Code Example
;This code turns on both clocks, selects the desired
; one, then turns on the Clock Monitor and Interrupts
;Mask for CMIE, CMON, ICGON, ICGS, ECGON, ECGS
; If Internal Clock desired, mask is $AF
start lda
#$AF
; If External Clock desired, mask is $BF
; If interrupts not desired mask is $2F int; $3F ext
;Other code here, such as writing the COP, since ECGS
; and ICGS may take some time to set.
loop
**
**
sta
icgcr
;Try to set CMIE. CMIE wont set until CMON set; CMON
; won’t set until ICGON, ICGS, ECGON, ECGS set.
brset 6,ICGCR,error ;Verify CMF is not set
cmpa
bne
icgcr
loop
;Check if ECGS set, then CMON set, then CMIE set
;Keep looping until CMIE is set.
Figure 8-8. Code Example for Enabling the Clock Monitor
Advance Information
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MC68HC908RFRK2
MOTOROLA
Internal Clock Generator Module (ICG)
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