Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
8.4.5 Clock Selection Circuit
The clock selection circuit, shown in Figure 8-5, contains two clock
switches which generate the oscillator output clock (CGMXCLK) from
either the internal clock (ICLK) or the external clock (ECLK). The clock
selection circuit also contains a divide-by-two circuit which creates the
clock generator output clock (CGMOUT), which generates the bus
clocks.
SELECT
OUTPUT
CS
CGMXCLK
ICLK
ICLK
ECLK
IOFF
SYNCHRONIZING
CLOCK
ECLK
DIV2
IOFF
SWITCHER
EOFF
EOFF
CGMOUT
FORCE_I
FORCE_E
RESET
V
SS
NAME
NAME
REGISTER BIT
NAME
TOP LEVEL SIGNAL
MODULE SIGNAL
Figure 8-5. Clock Selection Circuit Block Diagram
8.4.5.1 Clock Selection Switch
The clock select switch creates the oscillator output clock (CGMXCLK)
from either the internal clock (ICLK) or the external clock (ECLK), based
on the clock select bit (CS; set selects ECLK, clear selects ICLK). When
switching the CS bit, both ICLK and ECLK must be on (ICGON and
ECGON set). The clock being switched to must also be stable (ICGS or
ECGS set).
Advance Information
120
MC68HC908RFRK2
Internal Clock Generator Module (ICG)
MOTOROLA
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