Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
Functional Description
8.4.5.2 Clock Switching Circuit
To robustly switch between the internal clock (ICLK) and the external
clock (ECLK), the switch assumes the clocks are completely
asynchronous, so a synchronizing circuit is required to make the
transition (see Figure 8-6). When the clock select bit is changed, the
switch will continue to operate off the original clock for between 1 and 2
cycles as the select input transitions through one side of the
synchronizer. Next, the output will be held low for between 1 and 2
cycles of the new clock as the select input transitions through the other
side. Then the output starts switching at the new clock’s frequency. This
transition guarantees that no glitches will be seen on the output even
though the select input may change asynchronously to the clocks. The
unpredictably of the transition period is a necessary result of the
asynchronicity.
IOFF
D
Q
D
Q
DFF
DFF
CK
CK
QB
QB
ICLK
FORCE_I
OUTPUT
ECLK
FORCE_E
SELECT
EOFF
QB
QB
CK
D
CK
D
DFF
DFF
Q
Q
FORCE_I = Force internal; reset condition
FORCE_E = Force external
Figure 8-6. Synchronizing Clock Switcher Circuit Diagram
MC68HC908RFRK2
MOTOROLA
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Internal Clock Generator Module (ICG)
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