Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
NOTE: Although the clock monitor can be enabled only when the both clocks
are stable (ICGS or ECGS is set), the clock monitor will remain enabled
if one of the clocks goes unstable.
The clock monitor only works if the external slow (EXTSLOW) bit in the
configuration register is properly defined with respect to the external
frequency source.
The clock monitor circuit, shown in Figure 8-4, contains these blocks:
•
•
•
Clock monitor reference generator
Internal clock activity detector
External clock activity detector
8.4.4.1 Clock Monitor Reference Generator
The clock monitor uses a reference based on one clock source to
monitor the other clock source. The clock monitor reference generator
generates the external reference clock (EREF) based on the external
clock (ECLK) and the internal reference clock (IREF) based on the
internal clock (ICLK). To simplify the circuit, the low-frequency base
clock (IBASE) is used in place of ICLK because it always operates at or
near 307.2 kHz. For proper operation, EREF must be at least twice as
slow as IBASE and IREF must be at least twice as slow as ECLK.
To guarantee that IREF is slower than ECLK and EREF is slower than
IBASE, one of the signals is divided down. Which signal is divided and
by how much is determined by the external slow (EXTSLOW) bit in the
configuration register, according to the rules in Table 8-2. Note that each
signal (IBASE and ECLK) is always divided by four. A longer divider is
used on either IBASE or ECLK based on the EXTSLOW bit.
NOTE: If EXTSLOW is not set according to the rules defined in Table 8-2, the
clock monitor could switch clock sources unexpectedly.
Advance Information
116
MC68HC908RFRK2
MOTOROLA
Internal Clock Generator Module (ICG)
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