Freescale Semiconductor, Inc.
Internal Clock Generator Module (ICG)
Table 8-2. Clock Monitor Reference Divider Ratios
0
x
x
x
x
x
U
0
U
U
0
U
U
Off
U
0
0
0
Off
Off
0
U
Min
Max
Min
30 kHz
1.875 kHz
500 kHz
244 Hz
1.953 kHz
4096
(ECLK)
76.8 kHz
+/– 25%
x
x
x
x
x
x
0
1
1
x
0
1
Off
128*4
1*4
0
1*4
1*4
8 MHz
1 MHz
8 MHz
30 kHz
100 kHz
1.953 kHz
15.63 kHz
7.5 kHz
4096
(ECLK)
76.8 kHz
+/– 25%
Max
Min
4096
(IBASE)
75 Hz
+/– 25%
4.8 kHz
+/– 25%
16*4
Max
25.0 kHz
U: Unaffected. Refer to section of table where ICGON or ECGON is set to x (don’t care).
IBASE is always used as the internal frequency (307.2 kHz).
The long divider (divide by 4096) is also used as an external crystal
stabilization divider. The divider is reset when the external clock
generator is off (ECGEN is clear). When the external clock generator is
first turned on, the external clock generator stable bit (ECGS) will be
clear. This condition automatically selects ECLK as the input to the long
divider. The external stabilization clock (ESTBCLK) will be ECLK divided
by 4096. This timeout allows the crystal to stabilize. The falling edge of
ESTBCLK is used to set ECGS. (ECGS will set after a full 16 or 4096
cycles.) When ECGS is set, the divider returns to its normal function.
ESTBCLK may be generated by either IBASE or ECLK, but any clocking
will reinforce only the set condition. If ECGS is cleared because the clock
monitor determined that ECLK was inactive, the divider will revert to a
stabilization divider. Since this will change the EREF and IREF divide
ratios, it is important to turn the clock monitor off (CMON = 0) after
inactivity is detected to ensure valid recovery.
Advance Information
118
MC68HC908RFRK2
Internal Clock Generator Module (ICG)
MOTOROLA
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