Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
PORT A DATA REGISTER
PORT B DATA REGISTER
8
2
PORT C DATA REGISTER
PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
PORT D DATA DIRECTION REGISTER
UNIMPLEMENTED
3
4
UNIMPLEMENTED
SIOP CONTROL REGISTER
5
SIOP STATUS REGISTER
SIOP DATA REGISTER
UNIMPLEMENTED
6
UNIMPLEMENTED
UNIMPLEMENTED
7
UNIMPLEMENTED
RESERVED
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
8
INPUT CAPTURE MOST SIGNIFICANT BIT
INPUT CAPTURE LEAST SIGNIFICANT BIT
OUTPUT COMPARE MOST SIGNIFICANT BIT
OUTPUT COMPARE LEAST SIGNIFICANT BIT
TIMER MOST SIGNIFICANT BIT
TIMER LEAST SIGNIFICANT BIT
ALTERNATE COUNTER MOST SIGNIFICANT BIT
ALTERNATE COUNTER LEAST SIGNIFICANT BIT
EEPROM PROGRAMMING REGISTER
A/D CONVERTER DATA REGISTER
A/D CONVERTER CONTROL AND STATUS REGISTER
RESERVED
9
10
11
12
13
14
A
Figure 2-2. MC68HC805P18 I/O and Control Registers Memory Map
16
17
18
19
20
MEMORY
MC68HC805P18
2-4
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