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68HC705SB7 参数 Datasheet PDF下载

68HC705SB7图片预览
型号: 68HC705SB7
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 170 页 / 1982 K
品牌: FREESCALE [ Freescale ]
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GENERAL RELEASE SPECIFICATION  
August 27, 1998  
6.2  
WAIT MODE  
The WAIT instruction puts the MCU in a low power wait mode which consumes  
more power than the stop mode. The wait mode and has the following affects on  
the MCU:  
Enables interrupts by clearing the I bit in the condition code register.  
Enables external interrupts by setting the IRQE bit in the IRQ status and  
control register.  
Stops the CPU clock which drives the address and data buses, but  
allows the internal oscillator and its clock to continue to run and drive the  
Core Timer, programmable Timer, analog subsystem and SM-Bus.  
The WAIT instruction does not affect any other bits, registers or I/O lines.  
The following conditions restart the CPU clock and bring the MCU out of the wait  
mode:  
An external interrupt signal on the IRQ/V  
pin — A high to low  
PP  
transition on the IRQ/V  
pin loads the program counter with the  
PP  
contents of locations $1FFA and $1FFB.  
A programmable Timer interrupt — A programmable Timer interrupt  
driven by an input capture, output compare or timer overflow loads the  
program counter with the contents of locations $1FF6 and $1FF7.  
An SM-Bus interrupt — An SM-Bus interrupt driven by the completion of  
transmitted or received 8-bit data loads the program counter with the  
contents of locations $1FF4 and $1FF5.  
An analog subsystem interrupt — An analog subsystem interrupt driven  
by a voltage comparison loads the program counter with the contents of  
locations $1FF2 and $1FF3.  
A Core Timer interrupt — A Core Timer overflow or a real time interrupt  
loads the program counter with the contents of locations $1FF0 and  
$1FF1.  
A COP watchdog reset — A timeout of the COP watchdog resets the  
MCU and loads the program counter with the contents of locations  
$1FFE and $1FFF. Software can enable real time interrupts so that the  
MCU can periodically exit the wait mode to reset the COP watchdog.  
External reset — A logic zero on the RESET pin resets the MCU and  
loads the program counter with the contents of locations $1FFE and  
$1FFF.  
6.3  
DATA-RETENTION MODE  
In the data retention mode, the MCU retains RAM contents and CPU register con-  
tents at V  
voltages as low as 2.0 VDC. The data retention feature allows the  
DD  
MCU to remain in a low power consumption state during which it retains data, but  
the CPU cannot execute instructions.  
MOTOROLA  
6-4  
LOW POWER MODES  
MC68HC05SB7  
REV 2.1