August 27, 1998
GENERAL RELEASE SPECIFICATION
To put the MCU in the data retention mode:
1. Drive the RESET pin to a logic zero.
2. Lower the V
voltage. The RESET pin must remain low continuously
DD
during data retention mode.
To take the MCU out of the data retention mode:
1. Return V to normal operating voltage.
DD
2. Return the RESET pin to a logic one.
6.4
SLOW MODE
The Slow Mode feature permits a slow down of all the internal operations and thus
reduces power consumption. It is particularly useful while going to the WAIT
mode. Slow mode is enabled by setting the SCLK bit in the Miscellaneous Control
Register ($0B).
BIT 7
TSEN
0
BIT 6
LVRON
1
BIT 5
BIT 4
SCLK
0
BIT 3
CSSEL
0
BIT 2
TCSEL
0
BIT 1
BIT 0
MCR
R
0
COPON
0
ESVEN SMINLEV
$000B
W
reset:
0
0
U = UNAFFECTED BY RESET
Figure 6-2. Miscellaneous Control Register (MCR)
SCLK — Slow Clock
Setting this bit to one will slow down the internal oscillator. Setting this bit to
zero the system will run at the nominal bus speed (f /2). This bit is cleared
osc
during power-on or external reset.
1 = Slow clock selected:
Internal operating frequency, f =f
=f
/1600.
/2.
OP BUS OSC
0 = Normal clock selected:
Internal operating frequency, f =f
=f
OP BUS OSC
MC68HC05SB7
REV 2.1
LOW POWER MODES
MOTOROLA
6-5
FREESCALE [ Freescale ]
