August 27, 1998
GENERAL RELEASE SPECIFICATION
ADDR
REGISTER
Port A Data
PORTA
R/W BIT 7 BIT 6 BIT 5 BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
$0000
PA7
PB7
PC7
PA6
PB6
PC6
PA5
PB5
PC5
INV
PA4
PB4
PA3
PA2
PA1
PA0
W
R
Port B Data
PORTB
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
PB3
PB2
PB1
W
R
Port C Data
PORTC
PC4
W
R
Analog MUX 1
AMUX1
HOLD DHOLD
VREF
MUX3
MUX2
MUX1
MUX0
W
R
Port A Data Direction
DDRA
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
W
R
Port B Data Direction
DDRB
0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
W
R
Port C Data Direction
DDRC
0
0
0
0
DDRC7 DDRC6 DDRC5 DDRC4
W
R
Analog MUX 2
AMUX2
0
0
IREF
MUX7
0
MUX6
0
MUX5
MUX4
W
R
CTimer Status/Ctrl
CTSCR
CTOF
TMR7
RTIF
CTOFE
TMR5
RTIE
RT1
RT0
W
R
CTOFR RTIFR
CTimer Counter
CTCR
TMR6
TMR4
TMR3
TMR2
TMR1
TMR0
W
R
CSA Status/Control
CSASCR
0
CSIF
CSEN
X30
X10
CSCAL CDEN
CDIE
W
R
CSIFR
Misc Control
MCR
0
TSEN LVRON
SCLK CSSEL TCSEL ESVEN SMINLEV
W
R
COPON
VCO Adjust
VAR
VA4
0
VA3
VA2
0
VA1
VA0
0
W
R
IRQ Status/Ctrl
ISCR
IRQF
0
IRQE VCOEN LEVEL
W
R
IRQR
PEPROM Bit Select
PEBSR
PEB7
PEB7
0
PEB7
PEB4
0
PEB3
0
PEB2
0
PEB1
0
PEB0
W
R
PEPROM Status/Ctrl
PESCR
PEDATA
PEPZRF
PEPGM
W
unimplemented bits
reserved bits
Figure 2-3. MC68HC05SB7 I/O Registers $0000-$000F
MC68HC05SB7
REV 2.1
MEMORY
MOTOROLA
2-3
FREESCALE [ Freescale ]
