August 27, 1998
GENERAL RELEASE SPECIFICATION
1.6.9 ESV
This pin provides a switchable 5mA at V
(at worst case) to an external
OH
EEPROM. The ESVEN bit in the Miscellaneous Control Register enables/disables
the ESV pin.
BIT 7
TSEN
0
BIT 6
LVRON
1
BIT 5
BIT 4
SCLK
0
BIT 3
CSSEL
0
BIT 2
TCSEL
0
BIT 1
BIT 0
MCR
R
0
COPON
0
ESVEN SMINLEV
$000B
W
reset:
0
0
U = UNAFFECTED BY RESET
ESVEN — ESV Enable
This read/write bit selects whether ESV is enable or not. Reset clears the
ESVEN bit.
1 = ESV enabled.
0 = ESV disabled.
1.6.10 PA0-PA7 / PWM0-PWM3, SCL0-SCL1, SDA0-SDA1
These eight I/O lines comprise the Port A. The state of any pin is software pro-
grammable and all Port A lines are configured as inputs during power-on or reset.
PA0-PA3 are multiplexed with PWM outputs PWM0-PWM3. PA4-PA7 are multi-
plexed with the two SM-Bus channels - SCL0, SDA0 and SCL1, SDA1.
1.6.11 PB1-PB7 / TCAP, CS0-CS1, AN0-AN3
Pins PB2/CS0 and PB3/CS1 are only available when selected by a mask option.
These seven I/O lines comprise the Port B. The state of any pin is software pro-
grammable and all Port B lines are configured as input during power-on or at
reset.
PB1 is configured as the TCAP input pin for the 16-bit timer after a reset, and is
disabled by setting the ICEN bit in the Analog Control Register ($1D).
PB2 and PB3 (when selected) are multiplexed with CS0 and CS1 respectively,
from the current sense interrupt circuit. See section on Current Sense Amplifier for
more details.
PB4-PB7 are multiplexed with the analog input pins of the A/D converter. See sec-
tion on Analog Subsystem for more details.
1.6.12 PC4-PC7
These four I/O lines comprise the port C.The state of any pin is software program-
mable and all port C lines are configured as input during power-on or at reset.
MC68HC05SB7
REV 2.1
GENERAL DESCRIPTION
MOTOROLA
1-7
FREESCALE [ Freescale ]
