GENERAL RELEASE SPECIFICATION
August 27, 1998
2.2
INPUT/OUTPUT SECTION
The first 48 addresses of the memory space, $0000 – $002F, are the I/O section
as summarized in Figure 2-2. These are the addresses of the I/O control regis-
ters, status registers, and data registers. Reading from unimplemented locations
will return unknown states, and writing to unimplemented locations will be ignored.
One I/O register is located outside the 48-byte I/O section which is the computer
operating properly (COP) register, mapped at $1FF0.
The assignment of each control, status, and data bit in the I/O register space from
$0000 through $002F are given in Figure 2-3, Figure 2-4, and Figure 2-5.
Addr.
Register Name
Port A Data Register
Addr.
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
Register Name
Timer Counter Register MSB
Timer Counter Register LSB
Alternate Counter Register MSB
Alternate Counter Register LSB
Reserved
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
Port B Data Register
Port C Data Register
Analog MUX Register 1
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
Analog MUX Register 2
Analog Control Register
Analog Status Register
Reserved
Core Timer Status & Control Register
Core Timer Counter
SM-Bus Address Register
SM-Bus Frequency Select Register
SM-Bus Control Register
SM-Bus Status Register
SM-Bus Data Register
D/A Register 0 H
CSA Status/Control Register
Miscellaneous Control Register
VCO Adjust Register
IRQ Status & Control Register
Personality EPROM Bit Select Register
Personality EPROM Status & Control Reg.
Reserved
D/A Register 0 L
D/A Register 1 H
D/A Register 1 L
Reserved
D/A Register 2 H
Timer Control Register
D/A Register 2 L
Timer Status Register
D/A Register 3 H
Input Capture Register MSB
Input Capture Register LSB
Output Compare Register MSB
Output Compare Register LSB
D/A Register 3 L
MUX Channel Enable Register
Reserved
Reserved
Figure 2-2. MC68HC05SB7 I/O Registers
MOTOROLA
2-2
MEMORY
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
