August 27, 1998
GENERAL RELEASE SPECIFICATION
ADDR
REGISTER
SM-Bus Address
SMADR
R/W BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
$0020
SMAD7 SMAD6 SMAD5 SMAD4 SMAD3 SMAD2 SMAD1
W
R
SM-Bus Freq. Sel.
SMFDR
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
FD4
FD3
FD2
FD1
FD0
W
R
SM-Bus Control
SMCR
SMEN SMIEN SMSTA SMTX
TXAK
SMUX
SRW
W
R
SM-Bus Status
SMSR
SMCF SMAAS SMBB
SMAL
SMIF
RXAK
SMD0
W
R
SMAL clr
SMIF clr
SM-Bus Data
SMDR
SMD7
D9
SMD6
D8
SMD5
D7
SMD4
SMD3
D5
SMD2
D4
SMD1
W
R
D/A Register 0
DAC0
W
R
D6
D3
D1
D3
D1
D3
D1
D3
D1
D2
D0
D2
D0
D2
D0
D2
D0
D/A Register 0
DAC0
W
R
D/A Register 1
DAC1
W
R
D9
D9
D8
D8
D8
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D/A Register 1
DAC1
W
R
D/A Register 2
DAC2
W
R
D/A Register 2
DAC2
W
R
D/A Register 3
DAC3
W
R
D9
D/A Register 3
DAC3
W
R
MUX Channel Enable
MCER
PWM_I
DA3-E DA2-E DA1-E DA0-E
W
R
Reserved
Reserved
W
R
W
unimplemented bits
reserved bits
Figure 2-5. MC68HC05SB7 I/O Registers $0020-$002F
ADDR
REGISTER
COP Register
COPR
R/W BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
R
0
0
0
0
0
0
0
$1FF0
W
COPC
Figure 2-6. COP Register (COPR)
MC68HC05SB7
REV 2.1
MEMORY
MOTOROLA
2-5
FREESCALE [ Freescale ]
