GENERAL RELEASE SPECIFICATION
August 27, 1998
2.3
INTERRUPT VECTOR MAPPING
The interrupt vectors are contained in the upper memory addresses above $1FF0
as shown in Figure 2-2.
Addr.
$1FF0
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
Register Name
CDET INTERRUPT VECTOR (MSB)
CDET INTERRUPT VECTOR (LSB)
ANALOG INTERRUPT VECTOR (MSB)
ANALOG INTERRUPT VECTOR (LSB)
SM-BUS INTERRUPT VECTOR (MSB)
SM-BUS INTERRUPT VECTOR (LSB)
TIMER INTERRUPT VECTOR (MSB)
TIMER INTERRUPT VECTOR (LSB)
CTIMER INTERRUPT VECTOR (MSB)
CTIMER INTERRUPT VECTOR (LSB)
EXTERNAL IRQ VECTOR (MSB)
EXTERNAL IRQ VECTOR (LSB)
SWI VECTOR (MSB)
SWI VECTOR (LSB)
RESET VECTOR (MSB)
RESET VECTOR(LSB)
Figure 2-7. MC68HC05SB7 Interrupt Vector Mapping
2.4
2.5
ROM
There are a total of 6160 bytes of ROM on chip. This includes 6144 bytes of user
ROM with locations $0600 through $1DFF for the user program storage and
another 16 bytes for user vectors at locations $1FF0 through $1FFF.
RAM
The 224 addresses from $0040 to $011F serve as both the user RAM and the
stack RAM. The stack begins at address $00C0 and proceeds down to $00FF.
The stack pointer can access 64 locations from $00C0 to $00FF. Using the stack
area for data storage or temporary work locations requires care to prevent it from
being over written due to stacking from an interrupt or subroutine call. The CPU
uses five RAM bytes to save all CPU register contents before processing an inter-
rupt. During a subroutine call, the CPU uses two bytes to store the return address.
The stack pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines or multiple interrupt levels. The CPU
may overwrite data in the RAM during a subroutine or during the interrupt stacking
operation.
MOTOROLA
2-6
MEMORY
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
