GENERAL RELEASE SPECIFICATION
August 27, 1998
ADDR
REGISTER
R/W BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
W
R
$0010
Reserved
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Reserved
W
Timer Control
TCR
R
0
0
0
0
0
0
ICIE
W
OCIE
OCF
TOIE
TOF
IEDG
0
OLVL
0
Timer Status
TSR
R
ICF
W
Input Capture MSB
ICRH
R
W
R
ICRH7 ICRH6 ICRH5 ICRH4 ICRH3 ICRH2 ICRH1 ICRH0
ICRL7 ICRL6 ICRL5 ICRL4 ICRL3 ICRL2 ICRL1 ICRL0
Input Capture LSB
ICRL
W
R
Output Compare MSB
OCRH
OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
W
R
Output Compare LSB
OCRL
OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0
W
R
Timer Counter MSB
TMRH
W
R
Timer Counter LSB
TMRL
TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0
ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0
ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0
W
R
Alter. Counter MSB
ACRH
W
R
Alter. Counter LSB
ACRL
W
R
Reserved
W
R
Analog Control
ACR
CHG
CPF
ATD2
ATD1
ICEN
0
CPIE
0
CPEN
0
ISEN
0
W
R
Analog Status
ASR
0
0
W
R
CPFR
Reserved
W
unimplemented bits
reserved bits
Figure 2-4. MC68HC05SB7 I/O Registers $0010-$001F
MOTOROLA
2-4
MEMORY
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
