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68HC705JJ7_1 参数 Datasheet PDF下载

68HC705JJ7_1图片预览
型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Pa ra lle l Inp ut/ Outp ut  
7.3.2 Da ta Dire c tion Re g iste r A (DDRA)  
The contents of the port A data direction register (DDRA) determine  
whether each port A pin is an input or an output. Writing a logic one to a  
DDRA bit enables the output buffer for the associated port A pin. A  
DDRA bit set to a logic one also disables the pulldown device for that pin.  
Writing a logic zero to a DDRA bit disables the output buffer for the  
associated port A pin. The upper two bits always read as logical zeros.  
A reset initializes all DDRA bits to logic zeros, configuring all port A pins  
as inputs and disabling the voltage comparators from driving PA4 or  
PA5.  
$0004  
Read:  
Write:  
Reset:  
Bit 7  
0
6
0
5
4
3
2
1
Bit 0  
DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0  
0
0
0
0
0
0
0
0
= Unimplemented  
Figure 7-2. Data Direction Register A (DDRA)  
DDRA5–DDRA0 — Port A Data Direction Bits  
These read/write bits control port A data direction. Reset clears the  
DDRA5–DDRA0 bits.  
1 = Corresponding port A pin configured as output and pulldown  
device disabled  
0 = Corresponding port A pin configured as input  
General Release Specification  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
Parallel Input/Output  
For More Information On This Product,  
Go to: www.freescale.com  
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