Freescale Semiconductor, Inc.
Re se ts
5.5 Inte rna l Re se ts
The four internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, the low-voltage reset, and the
illegal address detector. Only the COP watchdog timer reset, low-
voltage reset, and illegal address detector will also assert the pulldown
device on the RESET pin for the duration of the reset function or for three
to four internal bus cycles, whichever is longer.
5.5.1 Powe r-On Re se t (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out); that
function can be performed by the LVR. Depending on the DELAY bit in
the mask option register (MOR), there is an oscillator stabilization delay
of 16 or 4064 internal bus cycles after the LPO becomes active.
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of the 16 or 4064 cycle delay, the
RST signal will remain in the reset condition until the other reset
condition(s) end.
POR will not activate the pulldown device on the RESET pin. V must
DD
drop below V
for the internal POR circuit to detect the next rise of
POR
V .
DD
5.5.2 Com p ute r Op e ra ting Prop e rly (COP) Re se t
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic zero to the COPC bit
of the COP register at location $1FF0. The COP register, shown in
Figure 5-2, is a write-only register that returns the contents of EPROM
location $1FF0 when read.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Resets
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