Freescale Semiconductor, Inc.
Re se ts
5.2 Introd uc tion
This section describes the five reset sources and how they initialize the
MCU. A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user defined reset vector address. The following conditions
produce a reset:
• Initial power-up of device (power-on reset)
• A logic zero applied to the RESET pin (external reset)
• Timeout of the COP watchdog (COP reset)
• Low voltage applied to the device (LVR reset)
• Fetch of an opcode from an address not in the memory map
(illegal address reset)
Figure 5-1 shows a block diagram of the reset sources and their
interaction.
MASK OPTION REGISTER ($1FF1)
INTERNAL DATA BUS
COP WATCHDOG
LOW-VOLTAGE RESET
POWER-ON RESET
V
DD
ILLEGAL ADDRESS RESET
INTERNAL
ADDRESS BUS
S
TO CPU
RST
RESET
D
AND
RESET
LATCH
SUBSYSTEMS
R
3-CYCLE
CLOCKED
1-SHOT
INTERNAL
CLOCK
Figure 5-1. Reset Sources
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Resets
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
