Freescale Semiconductor, Inc.
Resets
Internal Resets
$1FF0
Read:
Write:
Reset:
Bit 7
EPMSEC
U
6
OPT
U
5
4
3
2
1
Bit 0
COPC
U
U
U
U
U
U
= Unimplemented
U = Unaffected
Figure 5-2. COP and Security Register (COPR)
1
EPMSEC — EPROM Security
The EPMSEC bit is a write-only security bit to protect the contents of
the user EPROM code stored in locations $0700–$1FFF.
OPT — Optional Features
The OPT bit enables two additional features: direct drive by
comparator 1 output to PB4; and voltage offset capability to sample
capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC
prevents the COP watchdog from resetting the MCU. Reset clears the
COPC bit.
1 = No effect on COP watchdog timer
0 = Reset COP watchdog timer
The COP watchdog reset will assert the pulldown device to pull the
RESET pin low for three to four cycles of the internal bus.
The COP watchdog reset function can be enabled or disabled by
programming the COPEN bit in the MOR.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Resets
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
