Freescale Semiconductor, Inc.
Re se ts
5.6.5 16-Bit Prog ra m m a b le Tim e r
A reset has the following effects on the 16-bit programmable timer:
• Initializes the timer counter registers (TMRH and TMRL) to a value
of $FFFC
• Initializes the alternate timer counter registers (ACRH and ACRL)
to a value of $FFFC
• Clears all the interrupt enables and the output level bit (OLVL) in
the timer control register (TCR)
• Does not affect the input capture edge bit (IEDG) in the TCR
• Does not affect the interrupt flags in the timer status register (TSR)
• Does not affect the input capture registers (ICRH and ICRL)
• Does not affect the output compare registers (OCRH and OCRL)
5.6.6 Se ria l Inte rfa c e
A reset has the following effects on the serial interface:
• Clears all bits in the SIOP control register (SCR)
• Clears all bits in the SIOP status register (SSR)
• Does not affect the contents of the SIOP data register (SDR)
A reset, therefore, disables the SIOP and leaves the shared port B pins
as general I/O. Any pending interrupt flag is cleared and the SIOP
interrupt is disabled. Also the baud rate defaults to the slowest rate.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Resets
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