Freescale Semiconductor, Inc.
Resets
Power-On Reset
5.3 Powe r-On Re se t
A positive transition on the V pin generates a power-on reset. The
DD
power-on reset is strictly for conditions during powering up and cannot
be used to detect drops in power supply voltage.
A delay of 16 or 4064 internal bus cycles (t
) after the oscillator
CYC
becomes active allows the clock generator to stabilize. If the RESET pin
is at logic zero at the end of this multiple t time, the MCU remains in
CYC
the reset condition until the signal on the RESET pin goes to a logic one.
5.4 Exte rna l Re se t
A logic zero applied to the RESET pin for a minimum of one and one half
t
generates an external reset. This pin is connected to a Schmitt
cyc
trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. The external reset
occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold.
This active low input will generate the internal RST signal that resets the
CPU and peripherals.
The RESET pin can also be pulled to a low state by an internal pulldown
device that is activated by three internal reset sources. This RESET
pulldown device will only be asserted for three to four cycles of the
internal bus or as long as the internal reset source is asserted.
NOTE: Do not connect the RESET pin directly to V , as this may overload
DD
some power supply designs if the internal pulldown on the RESET pin
should activate. If an external reset function is not required, the RESET
pin should be left unconnected.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Resets
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