Freescale Semiconductor, Inc.
Electrical Specifications
Reset Characteristics
Internal
Reset1
RESET
Pin
2
cyc
t
4064 or 16 t
RPD
Internal
Clock3
Internal
Address
Bus3
1FFF
NEW PCH NEW PCL
1FFE
Internal
Data
NEW
PCH
NEW
PCL
Bus3
NOTES:
1. Represents the internal reset from low-voltage reset, illegal opcode fetch or COP watchdog timeout
2. Only if reset occurs during normal delay of 4064 tCYC or short delay option of 16 tCYC for initial power-up or stop
recovery.
3. Internal timing signal and data information not available externally
Figure 15-3. Internal Reset Timing Diagram
V
V
DD
LVRR
V
LVRF
Low
Voltage
Reset
RESET
Pin1
2
t
4064 or 16 t
cyc
RPD
Internal
Clock3
Internal
Address
Bus3
1FFF
NEW PCH NEW PCL
1FFE
Internal
Data
NEW
PCH
NEW
PCL
Bus3
NOTES:
1. RESET pin pulled down by internal device
2
Only if LVR occurs during normal delay of 4064 tCYC or short delay option of 16 tCYC for initial power-up or stop
recovery.
3
Internal timing signal and data information not available externally
Figure 15-4. Low-Voltage Reset Timing Diagram
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Electrical Specifications
General Release Specification
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