Freescale Semiconductor, Inc.
Electrical Specifications
SIOP Timing (VDD = 3.0 Vdc)
tSCK
tSCKL
SCK
tV
tHO
MSB
BIT 1
LSB
SDO
SDI
tS
MSB
LSB
VALID DATA
tH
Figure 15-1. SIOP Timing Diagram
15.16 SIOP Tim ing (VDD = 3.0 Vd c )
Characteristic
Frequency of Operation
Symbol
Min
Typ
Max
Unit
Master
Slave
f
f
0.25 x f
DC
0.25 x f
—
0.25 x f
525
SIOP(M)
OP
OP
OP
kHz
SIOP(S)
Cycle Time
Master
Slave
t
t
4.0 x t
—
4.0 x t
—
4.0 x t
CYC
SCK(M)
SCK(M)
CYC
CYC
µs
1.9
Clock (SCK) Low Time (f = 4.2 MHz)
t
932
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
OP
SCKL
SDO Data Valid Time
SDO Hold Time
SDI Setup Time
SDI Hold Time
NOTE:
t
400
—
V
t
0
HO
t
200
200
—
S
t
—
H
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Electrical Specifications
General Release Specification
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