Freescale Semiconductor, Inc.
Ele c tric a l Sp e c ific a tions
15.17 Re se t Cha ra c te ristic s
Characteristic
Symbol
Min
Typ
Max
Unit
Low-Voltage Reset
Rising Recovery Voltage
Falling Reset Voltage
LVR Hysteresis
V
V
V
2.4
2.3
100
3.4
3.3
—
4.4
4.3
—
V
V
mV
LVRR
LVRF
LVRH
POR Recovery Voltage (see Note 2)
V
0
—
100
mV
POR
POR V Slew Rate (see Note 2)
DD
Rising (see Note 2)
Falling (see Note 2)
S
S
—
—
—
—
0.1
0.05
V/µs
VDDR
VDDF
RESET Pulse Width (when Bus Clock Active)
t
1.5
3
—
—
—
4
t
t
RL
CYC
RESET Pulldown Pulse Width
(from Internal Reset)
t
RPD
CYC
NOTE:
1. +2.7 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. By design, not tested
1
OSC1
t
RL
RESET
2
4064 or 16 t
cyc
Internal
Clock3
Internal
Address
1FFE
1FFF
NEW PCH NEW PCL
Bus3
Internal
Data
NEW
PCH
NEW
PCL
Op
code
Bus3
NOTES:
1. Represents the internal gating of the OSC1 pin
2. Normal delay of 4064 tCYC or short delay option of 16 tCYC
3. Internal timing signal and data information not available externally
Figure 15-2. Stop Recovery Timing Diagram
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Electrical Specifications
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