Freescale Semiconductor, Inc.
Programmable Timer
Alternate Counter Registers (ACRH and ACRL)
$001A
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Bit 15
14
13
12
11
10
1
1
1
1
1
1
1
1
$001B
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
1
1
1
1
1
1
0
0
= Unimplemented
Figure 11-5. Alternate Counter Registers (ACRH and ACRL)
The ACRL latch is a transparent read of the LSB until a read of the
ACRH takes place. A read of the ACRH latches the LSB into the ACRL
location until the ACRL is again read. The latched value remains fixed
even if multiple reads of the ACRH take place before the next read of the
ACRL. Therefore, when reading the MSB of the timer at ACRH, the LSB
of the timer at ACRL must also be read to complete the read sequence.
During power-on reset (POR), the counter is initialized to $FFFC and
begins counting after the oscillator startup delay. Because the counter is
16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator
cycles).
Reading the ACRH and ACRL in any order or any number of times does
not have any effect on the 16-bit free-running counter or the TOF flag bit.
NOTE: To prevent interrupts from occurring between readings of the ACRH and
ACRL, set the I bit in the condition code register (CCR) before reading
ACRH and clear the I bit after reading ACRL.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Programmable Timer
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