Freescale Semiconductor, Inc.
Prog ra m m a b le Tim e r
11.3 Tim e r Re g iste rs (TMRH a nd TMRL)
The functional block diagram of the 16-bit free-running timer counter and
timer registers is shown in Figure 11-2. The timer registers include a
transparent buffer latch on the LSB of the 16-bit timer counter.
READ
TMRL
LATCH
TMRL ($0019)
TMR LSB
READ
TMRH
READ
TMRH ($0018)
($FFFC)
INTERNAL
CLOCK
(OSC ÷ 2)
RESET
÷ 4
16-BIT COUNTER
OVERFLOW (TOF)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REG.
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 11-2. Programmable Timer Block Diagram
The timer registers (TMRH and TMRL) shown in Figure 11-3 are read-
only locations which contain the current high and low bytes of the 16-bit
free-running counter. Writing to the timer registers has no effect. Reset
of the device presets the timer counter to $FFFC.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Programmable Timer
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