Freescale Semiconductor, Inc.
Prog ra m m a b le Tim e r
11.6 Outp ut Com p a re Re g iste rs (OCRH a nd OCRL)
The output compare function is a means of generating an output signal
when the 16-bit timer counter reaches a selected value as shown in
Figure 11-8. Software writes the selected value into the output compare
registers. On every fourth internal clock cycle (every eight oscillator
clock cycles) the output compare circuitry compares the value of the
free-running timer counter to the value written in the output compare
registers. When a match occurs, the timer transfers the output level
(OLVL) from the timer control register (TCR) to the PB4/AN4/TCMP pin.
Software can use the output compare register to measure time periods,
to generate timing delays, or to generate a pulse of specific duration or
a pulse train of specific frequency and duty cycle on the PB4/AN4/TCMP
pin.
R/W
OCRH
R/W
OCRL
OCRH ($0016)
OCRL ($0017)
EDGE
SELECT
DETECT
LOGIC
PB4
16-BIT COMPARATOR
AN4
TCMP
($FFFC)
INTERNAL
CLOCK
(OSC ÷ 2)
÷ 4
16-BIT COUNTER
OUTPUT COMPARE
(OCF)
TIMER
INTERRUPT
REQUEST
RESET
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 11-8. Timer Output Compare Block Diagram
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Programmable Timer
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
