Freescale Semiconductor, Inc.
Programmable Timer
Input Capture Registers (ICRH and ICRL)
The input capture registers are made up of two 8-bit read-only registers
(ICRH and ICRL) as shown in Figure 11-7. The input capture edge
detector contains a Schmitt trigger to improve noise immunity. The edge
that triggers the counter transfer is defined by the input edge bit (IEDG)
in the TCR. Reset does not affect the contents of the input capture
registers.
The result obtained by an input capture will be one count higher than the
value of the free-running timer counter preceding the external transition.
This delay is required for internal synchronization. Resolution is affected
by the prescaler, allowing the free-running timer counter to increment
once every four internal clock cycles (eight oscillator clock cycles).
$0014
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Bit 15
14
13
12
11
10
Unaffected by Reset
$0015
Read:
Write:
Reset:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Unaffected by Reset
= Unimplemented
Figure 11-7. Input Capture Registers (ICRH and ICRL)
Reading the ICRH inhibits future captures until the ICRL is also read.
Reading the ICRL after reading the timer status register (TSR) clears the
ICF flag bit. There is no conflict between reading the ICRL and transfers
from the free-running timer counters. The input capture registers always
contain the free-running timer counter value which corresponds to the
most recent input capture.
NOTE: To prevent interrupts from occurring between readings of the ICRH and
ICRL, set the I bit in the condition code register (CCR) before reading
ICRH and clear the I bit after reading ICRL.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Programmable Timer
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