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68HC705JJ7_1 参数 Datasheet PDF下载

68HC705JJ7_1图片预览
型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Analog Subsystem  
Analog Control Register  
8.4 Ana log Control Re g iste r  
The analog control register (ACR) controls the power-up, interrupt, and  
flag operation. The analog subsystem draws about 500 µA of current  
while it is operating. The resulting power consumption can be reduced  
by powering down the analog subsystem when not in use. This can be  
done by clearing three enable bits (ISEN, CP1EN, and CP2EN) in the  
ACR at $001D. Since these bits are cleared following a reset, the voltage  
comparators and the charge current source will be powered down  
following a reset of the device.  
The control bits in the ACR are shown in Figure 8-5. All the bits in this  
register are cleared by a reset of the device.  
$001D  
Read:  
Write:  
Reset:  
Bit 7  
CHG  
0
6
ATD2  
0
5
ATD1  
0
4
ICEN  
0
3
CPIE  
0
2
1
Bit 0  
ISEN  
0
CP2EN CP1EN  
0
0
Figure 8-5. Analog Control Register (ACR)  
CHG  
The CHG enable bit allows direct control of the charge current source  
and the discharge device; and also reflects the state of the discharge  
device. This bit is cleared by a reset of the device.  
1 = If the ISEN bit is also set the charge current source is sourcing  
current out of the PB0/AN0 pin. Writing a logical one enables  
the charging current out of the PB0/AN0 pin.  
0 = The discharge device is sinking current into the PB0/AN0 pin.  
Writing a logical zero disables the charging current and  
enables the discharging current into the PB0/AN0 pin, if the  
ISEN bit is also set.  
ATD1:2  
The ATD1:2 enable bits select one of the four operating modes used  
for making A/D conversions via the single-slope method.These four  
modes are given in Table 8-3. These bits have no effect if the ISEN  
enable bit is cleared. These bits are cleared by a reset of the device  
and thereby return the analog subsystem to the manual A/D  
conversion method.  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
General Release Specification  
Analog Subsystem  
For More Information On This Product,  
Go to: www.freescale.com  
 
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