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68HC705JJ7_1 参数 Datasheet PDF下载

68HC705JJ7_1图片预览
型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Analog Subsystem  
Analog Multiplex Register  
NOTE: Either comparator may generate an output flag when the inputs are  
exchanged due to a change in the state of the INV bit. It is therefore  
recommended that the INV bit not be changed while waiting for a  
comparator flag. Further, any changes to the state of the INV bit should  
be followed by writing a logical one to both the CPFR1 and CPFR2 bits  
to clear any extraneous CPF1 or CPF2 flags that may have occurred.  
VREF  
This read/write bit connects the channel select bus to V for making  
DD  
a reference voltage measurement. It cannot be selected if any of the  
other input sources to the channel select bus are selected as shown  
in Table 8-2. This bit is cleared by a reset of the device.  
1 = Channel select bus connected to V if all MUX1:4 are cleared.  
DD  
0 = Channel select bus cannot be connected to V .  
DD  
MUX1:4  
These are read/write bits that connect the analog subsystem pins to  
the channel select bus and voltage comparator 2 for purposes of  
making a voltage measurement. They can be selected individually or  
combined with any of the other input sources to the channel select  
bus as shown in Table 8-2.  
NOTE: The V  
voltage source shown in Figure 8-1 depicts a small offset  
AOFF  
voltage generated by the total chip current passing through the package  
bond wires and lead frame that are attached to the single V pin. This  
SS  
offset raises the internal V reference (AV ) in the analog subsystem  
SS  
SS  
with respect to the external V pin. Turning on the V MUX to the  
SS  
SS  
channel select bus connects it to this internal AV reference line.  
SS  
When making A/D conversions this AV offset gets placed on the  
SS  
external ramping capacitor since the discharge device on the PB0/AN0  
pin discharges the external capacitor to the internal AV line. Under  
SS  
these circumstances the positive input (+) to comparator 2 will always be  
higher than the negative input (–) until the negative input reaches the  
AV offset voltage plus any offset in comparator 2.  
SS  
Therefore, input voltages cannot be resolved if they are less than the  
sum of the AV offset and the comparator offset, because they will  
SS  
always yield a low output from the comparator.  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
General Release Specification  
Analog Subsystem  
For More Information On This Product,  
Go to: www.freescale.com  
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