Freescale Semiconductor, Inc.
Ana log Sub syste m
Table 8-3. A/D Conversion Options
A/D
A/D Options
Charge
Option
Control
Mode
Current Flow To/From PB0/AN0
ISEN ATD2 ATD1 CHG
Current
Source and
Discharge
Disabled
0
X
X
X
Current control disabled, no source or sink current
Disabled
Begin sinking current when the CHG bit is cleared
and continue to sink current until the CHG bit is set.
1
1
0
0
0
0
0
1
Manual
Charge and
Discharge
0
1
Begin sourcing current when the CHG bit is set and
continue to source current until the CHG bit is
cleared.
Begin sinking current when the CHG bit is cleared
and continue to sink current until the CHG bit is set.
(The CHG bit is cleared by writing a logical zero to
it or when the CPF2 flag bit is set.)
1
1
0
0
1
1
0
1
Manual
Charge and
Automatic
Discharge
Begin sourcing current when the CHG bit is set; and
continue to source current until the CHG bit is
cleared. (The CHG bit is set by writing a logical one
to it or cleared when the CPF2 flag bit is set.)
Automatic
Charge and
Discharge
(TOF–ICF)
Synchronized
to Timer
The CHG bit remains cleared until the next timer
TOF occurs.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2
3
The CHG bit remains set until the next timer ICF
occurs.
Automatic
Charge and
Discharge
(OCF–ICF)
Synchronized
to Timer
The CHG bit remains cleared until the next timer
OCF occurs.
The CHG bit remains set until the next timer ICF
occurs.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Analog Subsystem
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