Freescale Semiconductor, Inc.
Analog Subsystem
Analog Status Register
8.5 Ana log Sta tus Re g iste r
The analog status register (ASR) contains status and control of the
comparator flag bits. These bits in the ASR are shown in Figure 8-6. All
the bits in this register are cleared by a reset of the device.
$001E
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
CMP1
R
CPF2
CPF1
0
CPFR2
0
0
CPFR1
0
CMP2
COE1
VOFF
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 8-6. Analog Status Register (ASR)
CPF2
This read-only flag bit is edge sensitive to the rising output of
comparator 2. It is set when the voltage on the PB0/AN0 pin rises
above the voltage on sample capacitor which creates a positive edge
on the output of comparator 2, regardless of the state of the INV bit in
the AMUX register. This bit is reset by writing a logical one to the
CPFR2 reset bit in the ASR. This bit is cleared by a reset of the
device.
1 = A positive transition on the output of comparator 2 has occurred
since the last time the CPF2 flag has been cleared.
0 = A positive transition on the output of comparator 2 has not
occurred since the last time the CPF2 flag has been cleared.
CPF1
This read-only flag bit is edge sensitive to the rising output of
comparator 1. It is set when the voltage on the PB2/AN2 pin rises
above the voltage on the PN3/AN3/TCAP pin which creates a positive
edge on the output of comparator 1, regardless of the state of the INV
bit in the AMUX register. This bit is reset by writing a logical one to the
CPFR1 reset bit in the ASR. This bit is cleared by a reset of the
device.
1 = A positive transition on the output of comparator 1 has occurred
since the last time the CPF1 flag has been cleared.
0 = A positive transition on the output of comparator 1 has not
occurred since the last time the CPF1 flag has been cleared.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
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