Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
Internal Bus
Internal
Processor
Clock
High
Byte
Low
Byte
8-Bit
Buffer
/4
High Low
Byte Byte
$16
$17
Output
Compare
Register
High
Byte
Low
Byte
Input
Capture
Register
16-Bit Free
Running
Counter
$14
$15
$18
$19
Counter
Alternate
Register
$1A
$1B
Edge
Detect
Circuit
Overflow
Detect
Circuit
Output
Compare
Circuit
D
Q
CLK
Output
Level
Reg.
Timer
$13
Status ICF OCF TOF
Reg.
C
Timer
Control RESET
Reg.
$12
ICIE OCIE TOIE IEDG OLVL
Output Edge
Level Input
(TCMP) (TCAP)
Interrupt
Circuit
Figure 8-1. Timer Block Diagram
8.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter or
counter register, preceded by a prescaler that divides the internal processor clock
by four. The prescaler gives the timer a resolution of 2.0 microseconds if the
internal bus clock is 2.0 MHz. The counter is incremented during the low portion
of the internal bus clock. Software can read the counter at any time without
affecting its value.
The double-byte, free-running counter can be read from either of two locations,
$18-$19 (counter register) or $1A-$1B (counter alternate register). A read from
only the least significant byte (LSB) of the free-running counter ($19, $1B)
receives the count value at the time of the read. If a read of the free-running
counter or counter alternate register first addresses the most significant byte
(MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value
remains fixed after the first MSB read, even if the user reads the MSB several
TIMER
MC68HC05P4A
Rev. 2.0
8-2
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