Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8.5
Timer Status Register (TSR) $13
The TSR is a read-only register containing three status flag bits.
$13
ICF
U
OCF
U
TOF
U
0
0
0
0
0
0
0
0
0
0
RESET:
Figure 8-3. Timer Status Register
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TSR and input capture low register ($15) are
accessed
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the free-
running counter contents
0 = Flag cleared when TSR and output compare low register ($17) are
accessed
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to $0000
occurs
0 = Flag cleared when TSR and counter low register ($19) are accessed
Bits 0-4 — Not used
Always read zero
Accessing the timer status register satisfies the first condition required to clear
status bits. The remaining step is to access the register corresponding to the
status bit.
A problem can occur when using the timer overflow function and reading the free-
running counter at random times to measure an elapsed time. Without
incorporating the proper precautions into software, the timer overflow flag could
unintentionally be cleared if:
1. The timer status register is read or written when TOF is set, and
2. The LSB of the free-running counter is read but not for the purpose of
servicing the flag.
The counter alternate register at address $1A and $1B contains the same value
as the free-running counter (at address $18 and $19); therefore, this alternate
register can be read at any time without affecting the timer overflow flag in the
timer status register.
TIMER
MC68HC05P4A
Rev. 2.0
8-6
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