Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
times. This buffer is accessed when reading the free-running counter or counter
alternate register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter alternate
register, if the MSB is read, the LSB also must be read to complete the sequence.
The counter alternate register differs from the counter register in one respect:
Aread of the counter register MSB can clear the timer overflow flag (TOF).
Therefore, the counter alternate register can be read at any time without the
possibility of missing timer overflow interrupts due to clearing of the TOF.
The free-running counter is configured to $FFFC during reset and is always a
read-only register. During a power-on reset, the counter is also preset to $FFFC
and begins running after the oscillator start-up delay. Because the free-running
counter is 16 bits preceded by a fixed divided-by-four prescaler, the value in the
free-running counter repeats every 262,144 internal bus clock cycles. When the
counter rolls over from $FFFF to $0000, the TOF bit is set. An interrupt can also
be enabled when counter rollover occurs by setting its interrupt enable bit (TOIE).
8.2
Output Compare Register
The 16-bit output compare register is made up of two 8-bit registers at locations
$16 (MSB) and $17 (LSB). The output compare register is used for several
purposes, such as indicating when a period of time has elapsed. All bits are
readable and writable and are not altered by the timer hardware or reset. If the
compare function is not needed, the two bytes of the output compare register can
be used as storage locations.
The output compare register contents are compared with the contents of the free-
running counter continually, and if a match is found, the corresponding output
compare flag (OCF) bit is set and the corresponding output level (OLVL) bit is
clocked to an output level register. The output compare register values and the
output level bit should be changed after each successful comparison to establish
a new elapsed timeout. An interrupt can also accompany a successful output
compare provided the corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing the MSB
($16), the output compare function is inhibited until the LSB ($17) is also written.
The user must write both bytes (locations) if the MSB is written first. A write made
only to the LSB ($17) will not inhibit the compare function. The free-running
counter is updated every four internal bus clock cycles. The minimum time
required to update the output compare register is a function of the program rather
than the internal hardware.
The processor can write to either byte of the output compare register without
affecting the other byte. The output level (OLVL) bit is clocked to the output level
register regardless of whether the output compare flag (OCF) is set or clear.
TIMER
Rev. 2.0
8-3
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