Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
7.2.2 SIOP Status Register (SSR)
This register is located at address $000B and contains only two bits.
$0B
SPIF
0
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET:
Figure 7-4. SIOP Status Register
SPIF — Serial Peripheral Interface Flag
This bit is set upon occurrence of the last rising clock edge and indicates that a
data transfer has taken place. It has no effect on any further transmissions and
can be ignored without problem. SPIF is cleared by reading the SSR with SPIF
set followed by a read or write of the serial data register. If it is cleared before
the last edge of the next byte, it will be set again. Reset clears this bit.
DCOL — Data Collision
This is a read-only status bit which indicates that an invalid access to the data
register has been made. This can occur any time after the first falling edge of
SCK and before SPIF is set. A read or write of the data register during this time
will result in invalid data being transmitted or received.
DCOL is cleared by reading the status register with SPIF set followed by a read
or write of the data register. If the last part of the clearing sequence is done
after another transmission has been started, DCOL will be set again. If the
DCOL bit is set and the SPIF is not set, clearing the DCOL requires turning the
SIOP off then turning it back on. Reset also clears this bit.
7-4
Rev. 2.0
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