Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8.4
Timer Control Register (TCR) $12
The TCR is a read/write register containing five control bits. Three bits control
interrupts associated with the timer status register flags ICF, OCF, and TOF.
$12
ICIE
0
OCIE
0
TOIE
0
0
0
0
0
0
0
IEDG
0
OLVL
0
RESET:
Figure 8-2. Timer Control Register
ICIE — Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge
Value of input edge determines which level transition on TCAP pin will trigger
free-running counter transfer to the input capture register
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit (U=unaffected).
OLVL — Output Level
Value of output level is clocked into output level register by the next successful
output compare and will appear on the TCMP pin
1 = High output
0 = Low output
Bits 2, 3, and 4 — Not used
Always read zero
TIMER
Rev. 2.0
8-5
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