Register Descriptions
6.5.4
Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01D6.
Base + $6
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
1
6
1
5
0
4
1
3
0
2
1
1
1
0
0
Write
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
RESET
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$D01D.
Base + $7
Read
15
1
14
1
13
0
12
1
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
1
Write
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
1
RESET
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see Figure 6-8) corresponds to a functional group of pins. See
Table 2-2 to identify which pins can deactivate the internal pull-up resistor.
Base + $8 15
14
13
12
11
10
9
8
7
6
0
5
CTRL
0
4
0
3
JTAG
0
2
0
1
0
0
0
Read
Write
0
EMI_
MODE
PWMA1 CAN
RESET IRQ XBOOT PWMB PWMA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1
Reserved —Bit 15
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
PWMA1—Bit 14
This bit controls the pull-up resistors on the FAULTA3 pin.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
117
FREESCALE [ Freescale ]
