Register Descriptions
GPIOC_PER Register
GPIO Controlled
0
1
I/O Pad Control
SIM_ GPS Register
0
1
Quad Timer Controlled
SPI Controlled
Figure 6-10 Overall Control of GPIOC Pads Using SIM_GPS Control
1
Table 6-2 Control of GPIOC Pads Using SIM_GPS Control
Control Registers
Pin Function
Comments
GPIO Input
0
0
1
0
1
—
—
0
—
—
0
GPIO Output
Quad Timer Input / Quad
Decoder Input 2
—
See the “Switch Matrix for Inputs to the Timer”
table in the 56F8300 Peripheral User Manual
for the definition of timer inputs based on the
Quad Decoder mode configuration.
Quad Timer Output / Quad
Decoder Input 3
1
—
0
1
SPI input
1
1
—
—
1
1
—
—
See SPI controls for determining the direction
of each of the SPI pins.
SPI output
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control bits is
used for each pin.
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
Two Input/Output pins associated with GPIOD can function as GPIO, EMI (default peripheral) or CAN2
(NOT available on the 56F8167 device) signals. GPIO is the default and is enabled/disabled via the
GPIOD_PER, as shown in Figure 6-11 and Table 6-3. When GPIOD[1:0] are programmed to operate as
peripheral input/output, then the choice between EMI and CAN2 inputs/outputs is made here in the GPS.
56F8367 Technical Data, Rev. 9
Freescale Semiconductor
Preliminary
121
FREESCALE [ Freescale ]
