Add.
Offset
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
0
0
0
0
0
SIM_
CONTROL
EMI_ ONCE
MODE EBL0
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
$0
$1
$2
$3
$4
$5
$6
$7
$8
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
RSTSTS
SWR COPR EXTR POR
W
R
SIM_SCR0
SIM_SCR1
SIM_SCR2
SIM_SCR3
FIELD
W
R
FIELD
FIELD
FIELD
W
R
W
R
W
R
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
0
0
1
0
SIM_MSH_
ID
W
R
SIM_LSH_ID
W
R
PWMA
1
EMI_
MODE
PWMA
0
SIM_PUDR
Reserved
CAN
RESET IRQ XBOOT PWMB
CTRL
JTAG
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
CLKOSR
$A
$B
$C
$D
$E
$F
A23
0
A22
0
A21
0
A20 CLKDIS
CLKOSEL
C2
0
SIM_GPS
SIM_PCE
D1
D0
C3
C1
C0
W
R
PWM PWM
B
EMI
1
ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI1
SCI0 SPI1
SPI0
1
A
W
R
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
SIM_ISALH
SIM_ISALL
SIM_PCE2
ISAL[23:22]
W
R
ISAL[21:6]
W
R
0
0
0
0
0
0
CAN2
W
= Reserved
Figure 6-2 SIM Register Map Summary
6.5.1
SIM Control Register (SIM_CONTROL)
Base + $0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
Read
Write
EMI_ ONCE SW
MODE EBL
STOP_
DISABLE
WAIT_
DISABLE
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-3 SIM Control Register (SIM_CONTROL)
Reserved—Bits 15–7
6.5.1.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
56F8367 Technical Data, Rev. 9
114
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
