Peripheral Memory Mapped Registers
Table 4-10 External Memory Integration Registers Address Map
(EMI_BASE = $00 F020)
Register
Acronym
Address
Offset
Register Description
Reset Values
CSBAR 0
$0
Chip Select Base Address Register 0
0 x 0004 = 64K since
EXTBOOT = EMI_MODE
= 0
CSBAR 1
$1
Chip Select Base Address Register 1
0 x 0004 = 64K since
EMI_MODE = 0
CSBAR 2
CSBAR 3
CSBAR 4
CSBAR 5
CSBAR 6
CSBAR 7
CSOR 0
CSOR 1
CSOR 2
CSOR 3
CSOR 4
CSOR 5
CSOR 6
CSOR 7
CSTC 0
CSTC 1
CSTC 2
CSTC 3
CSTC 4
CSTC 5
CSTC 6
CSTC 7
BCR
$2
$3
Chip Select Base Address Register 2
Chip Select Base Address Register 3
Chip Select Base Address Register 4
Chip Select Base Address Register 5
Chip Select Base Address Register 6
Chip Select Base Address Register 7
Chip Select Option Register 0
$4
$5
$6
$7
$8
$9
Chip Select Option Register 1
$A
Chip Select Option Register 2
$B
Chip Select Option Register 3
$C
$D
$E
Chip Select Option Register 4
Chip Select Option Register 5
Chip Select Option Register 6
$F
Chip Select Option Register 7
$10
$11
$12
$13
$14
$15
$16
$17
$18
Chip Select Timing Control Register 0
Chip Select Timing Control Register 1
Chip Select Timing Control Register 2
Chip Select Timing Control Register 3
Chip Select Timing Control Register 4
Chip Select Timing Control Register 5
Chip Select Timing Control Register 6
Chip Select Timing Control Register 7
Bus Control Register
Table 4-11 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRA0_CMP1
$0
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
49
FREESCALE [ Freescale ]
