Peripheral Memory Mapped Registers
Table 4-11 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F040)
Register Acronym
Address Offset
$29
Register Description
Comparator Load Register 2
TMRA2_CMPLD2
TMRA2_COMSCR
$2A
Comparator Status and Control Register
Reserved
TMRA3_CMP1
TMRA3_CMP2
TMRA3_CAP
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
Compare Register 1
Compare Register 2
Capture Register
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_COMSCR
Table 4-12 Quad Timer B Registers Address Map
(TMRB_BASE = $00 F080)
Quad Timer B is NOT available in the 56F8145 device
Register Acronym
Address Offset
Register Description
Compare Register 1
TMRB0_CMP1
TMRB0_CMP2
TMRB0_CAP
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
Compare Register 2
Capture Register
TMRB0_LOAD
TMRB0_HOLD
TMRB0_CNTR
TMRB0_CTRL
TMRB0_SCR
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Reserved
TMRB0_CMPLD1
TMRB0_CMPLD2
TMRB0_COMSCR
TMRB1_CMP1
$10
Compare Register 1
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
51
FREESCALE [ Freescale ]
